1. Field of the Invention
The present invention relates to a semiconductor memory device, such as flash memory, for example.
2. Description of Related Art
Flash memory is known as a type of semiconductor memory device. The memory cells in flash memory each have a FAMOS (floating gate avalanche metal oxide semiconductor) transistor. These memory cells are normally arranged in a matrix formation.
General purpose flash memory comprises a plurality of word lines disposed in rows, a plurality of bit lines disposed in columns, and a single source line. This source line is grounded. Each FAMOS transistor is connected by the control gate to the corresponding word line, by the drain terminal to the corresponding bit line, and by the source terminal to the source line.
The rewriting of stored data is performed by injecting charge from the drain to the floating gate, or by discharging charge from the floating gate to the drain. When the rewrite control potential is applied to the word line, injection or discharge of charge by the floating gate is effected depending on the potential of the bit line and the stored data is rewritten thereby.
The reading of stored data is performed by applying the read control potential to the word line after the bit line is charged to the reference potential. When the read control potential is applied to the word line, the FAMOS transistor with charge stored in the floating gate becomes on and the FAMOS transistor without charge stored in the floating gate is kept in an off state. In the case where the FAMOS transistor is on, the charge in the bit line is discharged to ground through the source line and therefore the potential of the bit line becomes 0 V. Meanwhile, in the case where the FAMOS transistor is off, the potential of the bit line does not change. The potential of the bit line is output as the read data.
The rewriting speed for flash memory increases in proportion to the increase in the FN current density of the FAMOS transistor. The FN current density is the density of the current flowing between the floating gate and the n type drain.
However, when a FAMOS transistor is constituted so as to have a high FN current density, the read disturb resistance of the FAMOS transistor becomes poor. Read disturb resistance is the resistance to variation in the amount of charge stored when data are read. When the FN current density is increased, injection and discharge of charge in the floating gate occur easily when data are read. Poor read disturb resistance results in reduced reliability of the stored data.
It is an object of the present invention to provide a semiconductor memory device with high writing speeds and good read disturb resistance.
For this reason, the semiconductor memory device relating to the present invention comprises: a memory cell block having floating gate transistors arranged in a matrix; a plurality of first selector lines each connected to the control gates of the transistors in the same row; a plurality of second selector lines each connected to the first terminals of transistors in the same column; a common line connected to the second terminals of transistors in a plurality of rows or a plurality of columns; and a driver circuit for performing normal charging for supplying the read potential to the common line, and accelerated charging for temporarily increasing the quantity of the charge supplied to the common line.
The semiconductor memory device relating to the present invention charges the common line, not the second selector line with the driver circuit when data are read. Consequently, even if the current density between the first terminal and the floating gate is made higher, that is, even if the writing speed is made faster, the read disturb resistance of the transistor will not become poor.
In addition, in the semiconductor memory device relating to the present invention, the driver circuit has an accelerated charging function. Consequently, the reading time becomes short because the common line can be charged in a short period of time.